? semiconductor components industries, llc, 2017 january, 2017 ? rev. 1 1 publication order number: esd8504g/d esd8504g esd protection diode low capacitance array for high speed data lines the esd8504g is designed to protect high speed data lines from esd. ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. the flow?through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb 3.0/3.1. features ? low capacitance (0.5 pf max, i/o to gnd) ? protection for the following iec standards: iec 61000?4?2 (level 4) ? low esd clamping voltage ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? usb 3.0/3.1 ? esata ? displayport maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ?55 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) esd esd 25 25 kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. see application note and8308/d for further description of survivability specs. marking diagram device package shipping ordering information udfn10 case 517bb pin configuration and schematic www. onsemi.com ESD8504GMUTAG udfn10 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 4gm 4g = specific device code m = date code = pb?free package i/o i/o i/o i/o gnd n/c n/c n/c n/c gnd 145 23 10 7 6 98 (note: microdot may be in either location) i/o pin 1 i/o pin 2 i/o pin 4 i/o pin 5 pins 3, 8 = note: common gnd ? only minimum of 1 gnd connection required
esd8504g www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter v rwm working peak voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current v hold holding reverse voltage i hold holding reverse current r dyn dynamic resistance i pp maximum peak pulse current v c clamping voltage @ i pp v c = v hold + (i pp * r dyn ) i v v c v rwm v hold v br r dyn v c i r i t i hold ?i pp r dyn i pp v c = v hold + (i pp * r dyn ) electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 3.0 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 4.0 4.5 6.0 v reverse leakage current i r v rwm = 3.0 v, i/o pin to gnd 1.0 a holding reverse voltage v hold i/o pin to gnd 1.9 v holding reverse current i hold i/o pin to gnd 20 ma clamping voltage (note 1) v c iec61000?4?2, 8 kv contact see figures 1 and 2 v clamping voltage tlp (note 2) see figures 5 through 8 v c i pp = 8 a i pp = ?8 a iec 61000?4?2 level 2 equivalent ( 4 kv contact, 4 kv air) 4.75 ?5.5 v i pp = 16 a i pp = ?16 a iec 61000?4?2 level 4 equivalent ( 8 kv contact, 15 kv air) 7.0 ?8.5 dynamic resistance r dyn i/o pin to gnd gnd to i/o pin 0.3 0.4 junction capacitance (see figures 9 & 10) c j v r = 0 v, f = 1 mhz between i/o pins and gnd v r = 0 v, f = 2.5 ghz between i/o pins and gnd v r = 0 v, f = 1 mhz, between i/o pins 0.39 0.5 0.45 0.25 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 3 and 4 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?20 0 20 40 60 80 100 14 0 120 figure 1. iec61000?4?2 +8 kv contact esd clamping voltage figure 2. iec61000?4?2 ?8 kv contact clamping voltage ?20 0 20 40 60 80 100 140 120 90 time (ns) time (ns) voltage (v) voltage (v) 80 70 60 50 40 30 20 10 0 ?10 10
esd8504g www. onsemi.com 3 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000?4?2 spec figure 4. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8307/d ? characterization of esd clamping performance. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd8504g www. onsemi.com 4 figure 5. positive tlp i?v curve figure 6. negative tlp i?v curve note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000?4?2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. v c , voltage (v) v c , voltage (v) 9 3 18 6 4 2 0 0 5 10 15 20 ?3 ?5 ?1 ? 8 ?6 ?4 ?2 0 0 ?5 ?10 ?15 ?20 tlp current (a) tlp current (a) 57 ?7 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 7. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 8 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. for more information on tlp measurements and how to interpret them please refer to and9007/d. figure 7. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 8. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
esd8504g www. onsemi.com 5 figure 9. junction capacitance; v r = ?3.0 v ? 0 v, f = 1 mhz, i/o ? gnd, dv/dt = 214 mv/s figure 10. junction capacitance; v r = 0 v, f = 500 mhz ? 10 ghz v r , voltage (v) frequency (hz) 9.5e+09 6.5e+09 3.5e+09 5.0e+08 0 0.2 0.3 0.4 0.6 capacitance (pf) 0.5 0.1 0 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 0 1.0 1.5 2.0 3.0 2.5 0.5 ?0.5 capacitance (pf) with esd8504g without esd8504g figure 11. usb3.0 eye diagram with and without esd8504g. 5 gb/s see application note and9075/d for further description of eye diagram testing methodology.
esd8504g www. onsemi.com 6 figure 12. esd8504g insertion loss 10 frequency (mhz) 100 1000 10000 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 db interface data rate (gb/s) fundamental frequency (ghz) 3 rd harmonic frequency (ghz) esd8504g insertion loss (db) usb 3.0 5 2.5 (m1) 7.5 (m3) m1 = ?0.13 m3 = ?1.08 m2 = ?0.48 m4 = ?10.0 usb 3.1 10 5.0 (m2) 15 (m4)
esd8504g www. onsemi.com 7 figure 13. usb 3.0/3.1 standard layout diagram vbus stda_sstx+ d? stda_sstx? d+ gnd_drain gnd stda_ssrx+ stda_ssrx? usb 3.0/3.1 type a connector esd8504g esd7l5.0 pcb layout guidelines steps must be taken for proper placement and signal trace routing of the esd protection device in order to ensure the maximum esd survivability and signal integrity for the application. such steps are listed below. ? place the esd protection device as close as possible to the i/o connector to reduce the esd path to ground and improve the protection performance. ? in usb 3.0 applications, the esd protection device should be placed between the ac coupling capacitors and the i/o connector on the tx differential lanes as shown in figure 14. in this configuration, no dc current can flow through the esd protection device preventing any potential latch-up condition. for more information on latchup considerations, see below description on page 8. ? make sure to use differential design methodology and impedance matching of all high speed signal traces. ? use curved traces when possible to avoid unwanted reflections. ? keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ? place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk. figure 14. usb 3.0/3.1 connection diagram
esd8504g www. onsemi.com 8 latch-up considerations on semiconductor?s 8000 series of esd protection devices utilize a snap-back, scr type structure. by using this technology, the potential for a latch-up condition was taken into account by performing load line analyses of common high speed serial interfaces. example load lines for latch-up free applications and applications with the potential for latch-up are shown below with a generic iv characteristic of a snapback, scr type structured device overlaid on each. in the latch-up free load line case, the iv characteristic of the snapback protection device intersects the load-line in one unique point (v op , i op ). this is the only stable operating point of the circuit and the system is therefore latch-up free. please note that for usb 3.0 applications, esd8504g latch-up free considerations are explained in more detail in the above pcb layout guidelines. in the non-latch up free load line case, the iv characteristic of the snapback protection device intersects the load-line in two points (v opa , i opa ) and (v opb , i opb ). therefore in this case, the potential for latch-up exists if the system settles at (v opb , i opb ) after a transient. because of this, esd8504g should not be used for hdmi applications ? esd8104 or esd8040 have been designed to be acceptable for hdmi applications without latch-up. please refer to application note and9116/d for a more in-depth explanation of latch-up considerations using esd8000 series devices. figure 15. example load lines for latch-up free applications and applications with the potential for latch-up i v v dd i ssmax i op v op i v v dd i ssmax i opa v opa i opb v opb esd8504g latch?up free: usb 2.0 ls/fs, usb 2.0 hs, usb 3.0/3.1 ss, displayport esd8504g potential latch?up: hdmi 1.4/1.3a tmds table 1. summary of scr requirements for latch-up free applications application vbr (min) (v) ih (min) (ma) vh (min) (v) on semiconductor esd8000 series recommended pn hdmi 1.4/1.3a tmds 3.465 54.78 1.0 esd8104, esd8040 usb 2.0 ls/fs 3.301 1.76 1.0 esd8504g usb 2.0 hs 0.482 n/a 1.0 esd8504g usb 3.0/3.1 ss 2.800 n/a 1.0 esd8504g, esd8006 displayport 3.600 25.00 1.0 esd8504g, esd8006
esd8504g www. onsemi.com 9 package dimensions udfn10 2.5x1, 0.5p case 517bb issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. c seating plane d b e 0.10 c a3 a a1 2x 2x 0.10 c dim a min millimeters 0.45 a1 0.00 a3 0.13 ref b 0.15 d 2.50 bsc b2 0.35 e 1.00 bsc e 0.50 bsc pin one reference 0.08 c 0.10 c 10x a 0.10 c note 3 l e b2 b b 5 6 8x 1 10 10x 0.05 c 0.30 l *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.45 0.50 dimensions: millimeters 1.30 pitch 0.25 10x 0.55 0.05 0.25 0.45 0.40 max ??? ??? a1 a3 detail b mold cmpd exposed cu optional construction l1 detail a l optional constructions l --- l1 0.05 top view side view bottom view detail b detail a outline package a 2x recommended 2x 8x on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd8504g/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?
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